2024-12-01 12:55:20 +01:00
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module RISCAssembly : sig
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type register = {
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index : string
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2024-12-01 12:55:20 +01:00
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}
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2024-12-03 17:18:42 +01:00
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type label = string
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2024-12-01 12:55:20 +01:00
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type risci =
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| Nop
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| BRegOp of brop * register * register * register
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| BImmOp of biop * register * int * register
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| URegOp of urop * register * register
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| Load of register * register
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| LoadI of int * register
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2024-12-01 12:55:20 +01:00
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| Store of register * register
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| Jump of label
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| CJump of register * label * label
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| Label of label
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and brop =
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| Add
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| Sub
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| Mult
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| Div
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| Mod
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| Pow
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| And
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| Or
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| Eq
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| Less
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| LessEq
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| More
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| MoreEq
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and biop =
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| AddI
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| SubI
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| MultI
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| DivI
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| ModI
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| PowI
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| AndI
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| OrI
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| EqI
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| LessI
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| LessEqI
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| MoreI
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| MoreEqI
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and urop =
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| Not
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| Copy
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| Rand
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type t = {
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code : risci list;
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2024-12-27 21:11:38 +01:00
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inputval: int option;
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inputoutputreg: (register * register) option;
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}
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2024-12-01 12:55:20 +01:00
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2024-12-03 17:18:42 +01:00
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val pp_risci : out_channel -> risci -> unit
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val pp : out_channel -> t -> unit
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end
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val convert : CfgRISC.RISCCfg.t -> RISCAssembly.t
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