Semantics for RISC code

This commit is contained in:
elvis
2024-12-03 17:18:42 +01:00
parent efa6ed21c9
commit 08a8d07422
20 changed files with 771 additions and 86 deletions

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@ -1,9 +1,9 @@
module RISCAssembly : sig
type register = {
index : int
index : string
}
type label
type label = string
type risci =
| Nop
| BRegOp of brop * register * register * register
@ -48,8 +48,12 @@ module RISCAssembly : sig
| Copy
| Rand
type t = risci list
type t = {
code : risci list;
inputval: int option
}
val pp_risci : out_channel -> risci -> unit
val pp : out_channel -> t -> unit
end