Fixes defined variables, fixes live variables, implements reduces registers, fixes risc semantic

This commit is contained in:
elvis
2024-12-27 21:11:38 +01:00
parent f1b4c3a17d
commit 3be05222ab
15 changed files with 866 additions and 214 deletions

View File

@ -59,7 +59,8 @@ module RISCAssembly = struct
type t = {
code : risci list;
inputval: int option
inputval: int option;
inputoutputreg: (register * register) option;
}
let pp_risci (ppf: out_channel) (v: risci) : unit =
@ -285,4 +286,9 @@ let rec helper
let convert (prg: CfgRISC.RISCCfg.t) : RISCAssembly.t =
{code = (helper prg (Option.get prg.initial) [] |> fst |>
List.append ([Label "main"] : RISCAssembly.risci list));
inputval = prg.inputVal}
inputval = prg.inputVal;
inputoutputreg =
match prg.inputOutputVar with
None -> None
| Some (i, o) -> Some ({index = i}, {index = o})
}