Fixes defined variables, fixes live variables, implements reduces registers, fixes risc semantic

2024-12-27 21:11:38 +01:00
parent f1b4c3a17d
commit 3be05222ab
15 changed files with 866 additions and 214 deletions
--- a/lib/miniImp/RISC.mli
+++ b/lib/miniImp/RISC.mli
@ -50,7 +50,8 @@ module RISCAssembly : sig

  type t = {
    code : risci list;
-    inputval: int option
+    inputval: int option;
+    inputoutputreg: (register * register) option;
  }

  val pp_risci : out_channel -> risci -> unit