Implementing cfg for risc
This commit is contained in:
@ -28,14 +28,14 @@ module type C = sig
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nodes: NodeSet.t;
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edges: (Node.t * (Node.t option)) NodeMap.t;
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reverseEdges: (Node.t list) NodeMap.t;
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inputVal: elt option;
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outputVal: elt option;
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inputVal: int option;
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inputOutputVar: (string * string) option;
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initial: Node.t option;
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terminal: Node.t option;
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content: elt list NodeMap.t
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}
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val create : unit -> t
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val empty : t
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val merge : t -> t -> Node.t -> Node.t -> t
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val concat : t -> t -> t
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val addToLastNode : elt -> t -> t
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@ -50,20 +50,20 @@ module Make(M: PrintableType) = struct
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nodes: NodeSet.t;
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edges: (Node.t * (Node.t option)) NodeMap.t;
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reverseEdges: (Node.t list) NodeMap.t;
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inputVal: elt option;
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outputVal: elt option;
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inputVal: int option;
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inputOutputVar: (string * string) option;
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initial: Node.t option;
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terminal: Node.t option;
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content: elt list NodeMap.t
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}
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let create () : t =
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let empty : t =
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{ empty = true;
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nodes = NodeSet.empty;
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edges = NodeMap.empty;
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reverseEdges = NodeMap.empty;
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inputVal = None;
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outputVal = None;
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inputOutputVar = None;
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initial = None;
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terminal = None;
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content = NodeMap.empty }
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@ -93,7 +93,7 @@ module Make(M: PrintableType) = struct
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NodeMap.add_to_list exitNode cfg1terminal |>
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NodeMap.add_to_list exitNode cfg2terminal;
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inputVal = cfg1.inputVal;
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outputVal = cfg1.outputVal;
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inputOutputVar = cfg1.inputOutputVar;
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initial = Some entryNode;
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terminal = Some exitNode;
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content = NodeMap.union (fun _ -> failwith "Failed merging code of cfg.")
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@ -118,7 +118,7 @@ module Make(M: PrintableType) = struct
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cfg1.reverseEdges cfg2.reverseEdges |>
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NodeMap.add_to_list cfg2initial cfg1terminal;
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inputVal = cfg1.inputVal;
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outputVal = cfg1.outputVal;
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inputOutputVar = cfg1.inputOutputVar;
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initial = Some cfg1initial;
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terminal = Some cfg2terminal;
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content = NodeMap.union (fun _ -> failwith "Failed merging code of cfg.")
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@ -133,7 +133,7 @@ module Make(M: PrintableType) = struct
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edges = NodeMap.empty;
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reverseEdges = NodeMap.empty;
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inputVal = None;
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outputVal = None;
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inputOutputVar = None;
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initial = Some newnode;
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terminal = Some newnode;
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content = NodeMap.singleton newnode [newcontent]
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@ -168,13 +168,13 @@ module Make(M: PrintableType) = struct
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Printf.fprintf ppf "Input Value: ";
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(match c.inputVal with
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Some i -> Printf.fprintf ppf "%a" M.pp (i);
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Some i -> Printf.fprintf ppf "%d" i;
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| None -> Printf.fprintf ppf "None";);
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Printf.fprintf ppf "\n";
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Printf.fprintf ppf "Output Value: ";
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(match c.outputVal with
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Some i -> Printf.fprintf ppf "%a" M.pp (i);
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Printf.fprintf ppf "Input and Output Vars: ";
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(match c.inputOutputVar with
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Some (i, o) -> Printf.fprintf ppf "(in: %s, out: %s)" i o;
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| None -> Printf.fprintf ppf "None";);
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Printf.fprintf ppf "\n";
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@ -5,7 +5,9 @@ module type PrintableType = sig
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end
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module Node : sig
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type t
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type t = {
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id: int
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}
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val compare : t -> t -> int
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val create : unit -> t
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end
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@ -20,14 +22,14 @@ module type C = sig
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nodes: NodeSet.t;
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edges: (Node.t * (Node.t option)) NodeMap.t;
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reverseEdges: (Node.t list) NodeMap.t;
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inputVal: elt option;
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outputVal: elt option;
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inputVal: int option;
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inputOutputVar: (string * string) option;
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initial: Node.t option;
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terminal: Node.t option;
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content: elt list NodeMap.t
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}
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val create : unit -> t
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val empty : t
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val merge : t -> t -> Node.t -> Node.t -> t
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val concat : t -> t -> t
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val addToLastNode : elt -> t -> t
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@ -76,8 +76,8 @@ let rec convert_c (prevcfg: SSCfg.t) (prg: Types.c_exp) : SSCfg.t =
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cfg2
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| If (b, c1, c2) ->
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let convertedb = convert_b b in
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let cfg1 = convert_c (SSCfg.create ()) c1 in
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let cfg2 = convert_c (SSCfg.create ()) c2 in
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let cfg1 = convert_c SSCfg.empty c1 in
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let cfg2 = convert_c SSCfg.empty c2 in
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let entrynode = Node.create () in
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let exitnode = Node.create () in
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let newcfg = SSCfg.merge cfg1 cfg2 entrynode exitnode in
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@ -88,7 +88,7 @@ let rec convert_c (prevcfg: SSCfg.t) (prg: Types.c_exp) : SSCfg.t =
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NodeMap.add_to_list exitnode (SimpleSkip) }
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| While (b, c) ->
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let convertedb = convert_b b in
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let cfg = convert_c (SSCfg.create ()) c in
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let cfg = convert_c SSCfg.empty c in
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let cfginitial = Option.get cfg.initial in
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let cfgterminal = Option.get cfg.terminal in
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let entrynode = Node.create () in
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@ -109,17 +109,17 @@ let rec convert_c (prevcfg: SSCfg.t) (prg: Types.c_exp) : SSCfg.t =
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NodeMap.add_to_list exitnode guardnode |>
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NodeMap.add_to_list guardnode cfgterminal;
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inputVal = prevcfg.inputVal;
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outputVal = prevcfg.outputVal;
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inputOutputVar = prevcfg.inputOutputVar;
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initial = Some entrynode;
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terminal = Some exitnode;
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content = NodeMap.add_to_list guardnode (SimpleGuard (convertedb)) cfg.content |>
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NodeMap.add_to_list exitnode (SimpleSkip)
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} |> SSCfg.concat prevcfg
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| For (assignment, guard, increment, body) ->
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let cfgassignment = convert_c (SSCfg.create ()) assignment in
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let cfgassignment = convert_c SSCfg.empty assignment in
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let convertedguard = convert_b guard in
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let cfgincrement = convert_c (SSCfg.create ()) increment in
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let cfgbody = convert_c (SSCfg.create ()) body in
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let cfgincrement = convert_c SSCfg.empty increment in
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let cfgbody = convert_c SSCfg.empty body in
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let prevassignment = SSCfg.concat prevcfg cfgassignment in
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let bodyincrement = SSCfg.concat cfgbody cfgincrement in
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@ -141,7 +141,7 @@ let rec convert_c (prevcfg: SSCfg.t) (prg: Types.c_exp) : SSCfg.t =
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NodeMap.add_to_list exitnode guardnode |>
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NodeMap.add_to_list guardnode cfgterminal;
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inputVal = prevcfg.inputVal;
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outputVal = prevcfg.outputVal;
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inputOutputVar = prevcfg.inputOutputVar;
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initial = Some guardnode;
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terminal = Some exitnode;
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content = NodeMap.add_to_list guardnode (SimpleGuard (convertedguard)) bodyincrement.content |>
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@ -174,9 +174,9 @@ and convert_a (prg: Types.a_exp) : SimpleStatements.simpleArithmetic =
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| Rand (a) -> SimpleRand (convert_a a)
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let convert (prg: Types.p_exp) : SSCfg.t =
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let result =
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match prg with
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| Main (_, _, exp) ->
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convert_c (SSCfg.create ()) exp
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in
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{result with inputVal = None; outputVal = None}
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match prg with
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| Main (i, o, exp) ->
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{(convert_c SSCfg.empty exp) with inputOutputVar = Some (i, o)}
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let convert_io (prg: Types.p_exp) (i: int) : SSCfg.t =
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{(convert prg) with inputVal = Some i}
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@ -32,3 +32,4 @@ end
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module SSCfg : Cfg.C with type elt = SimpleStatements.t
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val convert : Types.p_exp -> SSCfg.t
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val convert_io : Types.p_exp -> int -> SSCfg.t
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459
lib/miniImp/CfgRISC.ml
Normal file
459
lib/miniImp/CfgRISC.ml
Normal file
@ -0,0 +1,459 @@
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module RISCSimpleStatements = struct
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type register = {
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index: int
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}
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type t =
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| Nop
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| BRegOp of brop * register * register * register
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| BImmOp of biop * register * int * register
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| URegOp of urop * register * register
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| Load of register * register
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| LoadI of register * int
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| Store of register * register
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and brop =
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| Add
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| Sub
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| Mult
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| Div
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| Mod
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| Pow
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| And
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| Or
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| Eq
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| Less
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| LessEq
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| More
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| MoreEq
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and biop =
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| AddI
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| SubI
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| MultI
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| DivI
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| ModI
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| PowI
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| AndI
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| OrI
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| EqI
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| LessI
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| LessEqI
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| MoreI
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| MoreEqI
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and urop =
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| Not
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| Copy
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| Rand
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let pp (ppf: out_channel) (v: t) : unit =
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let rec pp_t (ppf: out_channel) (v: t) : unit =
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match v with
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Nop -> Printf.fprintf ppf "nop"
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| BRegOp (b, r1, r2, r3) -> Printf.fprintf ppf "%a r%d r%d => r%d" pp_brop b r1.index r2.index r3.index
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| BImmOp (b, r1, i, r3) -> Printf.fprintf ppf "%a r%d %d => r%d" pp_biop b r1.index i r3.index
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| URegOp (u, r1, r2) -> Printf.fprintf ppf "%a r%d => r%d" pp_urop u r1.index r2.index
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| Load (r1, r2) -> Printf.fprintf ppf "load r%d => r%d" r1.index r2.index
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| LoadI (r2, i) -> Printf.fprintf ppf "loadi %d => r%d" i r2.index
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| Store (r1, r2) -> Printf.fprintf ppf "store r%d => r%d" r1.index r2.index
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and pp_brop (ppf: out_channel) (v: brop) : unit =
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match v with
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Add -> Printf.fprintf ppf "Add"
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| Sub -> Printf.fprintf ppf "Sub"
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| Mult -> Printf.fprintf ppf "Mult"
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| Div -> Printf.fprintf ppf "Div"
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| Mod -> Printf.fprintf ppf "Mod"
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| Pow -> Printf.fprintf ppf "Pow"
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| And -> Printf.fprintf ppf "And"
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| Or -> Printf.fprintf ppf "Or"
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| Eq -> Printf.fprintf ppf "Eq"
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| Less -> Printf.fprintf ppf "Less"
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| LessEq -> Printf.fprintf ppf "LessEq"
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| More -> Printf.fprintf ppf "More"
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| MoreEq -> Printf.fprintf ppf "MoreEq"
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and pp_biop (ppf: out_channel) (v: biop) : unit =
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match v with
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AddI -> Printf.fprintf ppf "AddI"
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| SubI -> Printf.fprintf ppf "SubI"
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| MultI -> Printf.fprintf ppf "MultI"
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| DivI -> Printf.fprintf ppf "DivI"
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| ModI -> Printf.fprintf ppf "ModI"
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| PowI -> Printf.fprintf ppf "PowI"
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| AndI -> Printf.fprintf ppf "AndI"
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| OrI -> Printf.fprintf ppf "OrI"
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| EqI -> Printf.fprintf ppf "EqI"
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| LessI -> Printf.fprintf ppf "LessI"
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| LessEqI -> Printf.fprintf ppf "LessEqI"
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| MoreI -> Printf.fprintf ppf "MoreI"
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| MoreEqI -> Printf.fprintf ppf "MoreEqI"
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and pp_urop (ppf: out_channel) (v: urop) : unit =
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match v with
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Not -> Printf.fprintf ppf "Nop"
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| Copy -> Printf.fprintf ppf "Copy"
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| Rand -> Printf.fprintf ppf "Rand"
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in
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pp_t ppf v
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let pplist (ppf: out_channel) (l: t list) : unit =
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List.iter (fun x -> pp ppf x; Printf.printf "; ") l
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end
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module RISCCfg = Cfg.Make(RISCSimpleStatements)
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let globalcounter = ref 0
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module RegisterMap = struct
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type m = {
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assignments: int Types.VariableMap.t
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}
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let _get_opt_register (x: Types.variable) (m: m) : RISCSimpleStatements.register option =
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Option.bind
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(Types.VariableMap.find_opt x m.assignments)
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(fun (x: int) : RISCSimpleStatements.register option -> Some {index = x})
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let get_or_set_register (x: Types.variable) (m: m) : RISCSimpleStatements.register * m =
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match Types.VariableMap.find_opt x m.assignments with
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None ->
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( globalcounter := !globalcounter + 1;
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({index = !globalcounter}, {assignments = Types.VariableMap.add x !globalcounter m.assignments}) )
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| Some i -> ({index = i}, m)
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let get_fresh_register (m: m) : RISCSimpleStatements.register * m * Types.variable =
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globalcounter := !globalcounter + 1;
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let freshvariable = string_of_int !globalcounter in
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({index = !globalcounter},
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{assignments = Types.VariableMap.add freshvariable !globalcounter m.assignments},
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freshvariable)
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let empty : m =
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{assignments = Types.VariableMap.empty}
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(* let pp (ppx) (m: m) : unit = *)
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(* Printf.fprintf ppx "RegisterMap contents: "; *)
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(* List.iter (fun (n, v) -> Printf.fprintf ppx "%s -> %d, " n v) (Types.VariableMap.to_list m.assignments); *)
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(* Printf.fprintf ppx "\n"; *)
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end
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let rec c_ss_t
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(ss: CfgImp.SimpleStatements.t)
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(m: RegisterMap.m)
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(convertedcode: RISCSimpleStatements.t list)
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: RISCSimpleStatements.t list * RegisterMap.m =
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match ss with
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SimpleSkip -> (Nop :: convertedcode, m)
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| SimpleAssignment (v, sa) -> (
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let r1, m = RegisterMap.get_or_set_register v m in
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c_ss_sa sa m convertedcode r1
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)
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| SimpleGuard (b) -> (
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let returnreg, m, _returnregvar = RegisterMap.get_fresh_register m in
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c_ss_sb b m convertedcode returnreg
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)
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and c_ss_sb
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(ss: CfgImp.SimpleStatements.simpleBoolean)
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(m: RegisterMap.m)
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(convertedcode: RISCSimpleStatements.t list)
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(register: RISCSimpleStatements.register)
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: RISCSimpleStatements.t list * RegisterMap.m =
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match ss with
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SimpleBoolean (b) -> (
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let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
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if b then
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(LoadI (partialresreg, 1) :: convertedcode, m)
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else
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(LoadI (partialresreg, 0) :: convertedcode, m)
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)
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| SimpleBAnd (b1, b2) -> (
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match (b1, b2) with
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| (SimpleBoolean (true), b)
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| (b, SimpleBoolean (true)) -> (
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c_ss_sb b m convertedcode register
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)
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| (SimpleBoolean (false), _)
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| (_, SimpleBoolean (false)) -> (
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(LoadI (register, 0) :: convertedcode, m)
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)
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| (_, _) -> (
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let partialresreg1, m, _partialresvar1 = RegisterMap.get_fresh_register m in
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let partialresreg2, m, _partialresvar2 = RegisterMap.get_fresh_register m in
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let convertedcode, m = c_ss_sb b1 m convertedcode partialresreg1 in
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let convertedcode, m = c_ss_sb b2 m convertedcode partialresreg2 in
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(BRegOp (And, partialresreg1, partialresreg2, register) :: convertedcode, m)
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)
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)
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| SimpleBOr (b1, b2) -> (
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match (b1, b2) with
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| (SimpleBoolean (false), b)
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| (b, SimpleBoolean (false)) -> (
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c_ss_sb b m convertedcode register
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)
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| (SimpleBoolean (true), _)
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| (_, SimpleBoolean (true)) -> (
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(LoadI (register, 1) :: convertedcode, m)
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)
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| (_, _) -> (
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let partialresreg1, m, _partialresvar1 = RegisterMap.get_fresh_register m in
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let partialresreg2, m, _partialresvar2 = RegisterMap.get_fresh_register m in
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let convertedcode, m = c_ss_sb b1 m convertedcode partialresreg1 in
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let convertedcode, m = c_ss_sb b2 m convertedcode partialresreg2 in
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(BRegOp (Or, partialresreg1, partialresreg2, register) :: convertedcode, m)
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)
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)
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| SimpleBNot (b) -> (
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match (b) with
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| SimpleBoolean (b) ->(
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if b then
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(LoadI (register, 0) :: convertedcode, m)
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else
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(LoadI (register, 1) :: convertedcode, m)
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)
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| _ -> (
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let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
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let convertedcode, m = c_ss_sb b m convertedcode partialresreg in
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(URegOp (Not, partialresreg, register) :: convertedcode, m)
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)
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)
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| SimpleBCmp (a1, a2) -> (
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match (a1, a2) with
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| (SimpleInteger (i), a)
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| (a, SimpleInteger (i)) -> (
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let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
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let convertedcode, m = c_ss_sa a m convertedcode partialresreg in
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(BImmOp (EqI, partialresreg, i, register) :: convertedcode, m)
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)
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| (_, _) -> (
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let partialresreg1, m, _partialresvar1 = RegisterMap.get_fresh_register m in
|
||||
let partialresreg2, m, _partialresvar2 = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a1 m convertedcode partialresreg1 in
|
||||
let convertedcode, m = c_ss_sa a2 m convertedcode partialresreg2 in
|
||||
(BRegOp (Eq, partialresreg1, partialresreg2, register) :: convertedcode, m)
|
||||
)
|
||||
)
|
||||
| SimpleBCmpLess (a1, a2) -> (
|
||||
match (a1, a2) with
|
||||
| (SimpleInteger (i), a) -> (
|
||||
let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a m convertedcode partialresreg in
|
||||
(BImmOp (MoreI, partialresreg, i, register) :: convertedcode, m)
|
||||
)
|
||||
| (a, SimpleInteger (i)) -> (
|
||||
let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a m convertedcode partialresreg in
|
||||
(BImmOp (LessI, partialresreg, i, register) :: convertedcode, m)
|
||||
)
|
||||
| (_, _) -> (
|
||||
let partialresreg1, m, _partialresvar1 = RegisterMap.get_fresh_register m in
|
||||
let partialresreg2, m, _partialresvar2 = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a1 m convertedcode partialresreg1 in
|
||||
let convertedcode, m = c_ss_sa a2 m convertedcode partialresreg2 in
|
||||
(BRegOp (Less, partialresreg1, partialresreg2, register) :: convertedcode, m)
|
||||
)
|
||||
)
|
||||
| SimpleBCmpLessEq (a1, a2) -> (
|
||||
match (a1, a2) with
|
||||
| (SimpleInteger (i), a) -> (
|
||||
let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a m convertedcode partialresreg in
|
||||
(BImmOp (MoreEqI, partialresreg, i, register) :: convertedcode, m)
|
||||
)
|
||||
| (a, SimpleInteger (i)) -> (
|
||||
let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a m convertedcode partialresreg in
|
||||
(BImmOp (LessEqI, partialresreg, i, register) :: convertedcode, m)
|
||||
)
|
||||
| (_, _) -> (
|
||||
let partialresreg1, m, _partialresvar1 = RegisterMap.get_fresh_register m in
|
||||
let partialresreg2, m, _partialresvar2 = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a1 m convertedcode partialresreg1 in
|
||||
let convertedcode, m = c_ss_sa a2 m convertedcode partialresreg2 in
|
||||
(BRegOp (LessEq, partialresreg1, partialresreg2, register) :: convertedcode, m)
|
||||
)
|
||||
)
|
||||
| SimpleBCmpGreater (a1, a2) -> (
|
||||
match (a1, a2) with
|
||||
| (SimpleInteger (i), a) -> (
|
||||
let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a m convertedcode partialresreg in
|
||||
(BImmOp (LessI, partialresreg, i, register) :: convertedcode, m)
|
||||
)
|
||||
| (a, SimpleInteger (i)) -> (
|
||||
let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a m convertedcode partialresreg in
|
||||
(BImmOp (MoreI, partialresreg, i, register) :: convertedcode, m)
|
||||
)
|
||||
| (_, _) -> (
|
||||
let partialresreg1, m, _partialresvar1 = RegisterMap.get_fresh_register m in
|
||||
let partialresreg2, m, _partialresvar2 = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a1 m convertedcode partialresreg1 in
|
||||
let convertedcode, m = c_ss_sa a2 m convertedcode partialresreg2 in
|
||||
(BRegOp (More, partialresreg1, partialresreg2, register) :: convertedcode, m)
|
||||
)
|
||||
)
|
||||
| SimpleBCmpGreaterEq (a1, a2) -> (
|
||||
match (a1, a2) with
|
||||
| (SimpleInteger (i), a) -> (
|
||||
let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a m convertedcode partialresreg in
|
||||
(BImmOp (LessEqI, partialresreg, i, register) :: convertedcode, m)
|
||||
)
|
||||
| (a, SimpleInteger (i)) -> (
|
||||
let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a m convertedcode partialresreg in
|
||||
(BImmOp (MoreEqI, partialresreg, i, register) :: convertedcode, m)
|
||||
)
|
||||
| (_, _) -> (
|
||||
let partialresreg1, m, _partialresvar1 = RegisterMap.get_fresh_register m in
|
||||
let partialresreg2, m, _partialresvar2 = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a1 m convertedcode partialresreg1 in
|
||||
let convertedcode, m = c_ss_sa a2 m convertedcode partialresreg2 in
|
||||
(BRegOp (MoreEq, partialresreg1, partialresreg2, register) :: convertedcode, m)
|
||||
)
|
||||
)
|
||||
|
||||
and c_ss_sa
|
||||
(ss: CfgImp.SimpleStatements.simpleArithmetic)
|
||||
(m: RegisterMap.m)
|
||||
(convertedcode: RISCSimpleStatements.t list)
|
||||
(register: RISCSimpleStatements.register)
|
||||
: RISCSimpleStatements.t list * RegisterMap.m =
|
||||
match ss with
|
||||
SimpleVariable (x) -> (
|
||||
let r1, m = RegisterMap.get_or_set_register x m in
|
||||
(Load (r1, register) :: convertedcode, m)
|
||||
)
|
||||
| SimpleInteger (i) -> (LoadI (register, i) :: convertedcode, m)
|
||||
| SimplePlus (a1, a2) -> (
|
||||
match (a1, a2) with
|
||||
| (SimpleInteger (i), a)
|
||||
| (a, SimpleInteger (i)) -> (
|
||||
let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a m convertedcode partialresreg in
|
||||
(BImmOp (AddI, partialresreg, i, register) :: convertedcode, m)
|
||||
)
|
||||
| (_, _) -> (
|
||||
let partialresreg1, m, _partialresvar1 = RegisterMap.get_fresh_register m in
|
||||
let partialresreg2, m, _partialresvar2 = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a1 m convertedcode partialresreg1 in
|
||||
let convertedcode, m = c_ss_sa a2 m convertedcode partialresreg2 in
|
||||
(BRegOp (Add, partialresreg1, partialresreg2, register) :: convertedcode, m)
|
||||
)
|
||||
)
|
||||
| SimpleMinus (a1, a2) -> (
|
||||
match (a1, a2) with
|
||||
| (a, SimpleInteger (i)) -> (
|
||||
let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a m convertedcode partialresreg in
|
||||
(BImmOp (SubI, partialresreg, i, register) :: convertedcode, m)
|
||||
)
|
||||
| (_, _) -> (
|
||||
let partialresreg1, m, _partialresvar1 = RegisterMap.get_fresh_register m in
|
||||
let partialresreg2, m, _partialresvar2 = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a1 m convertedcode partialresreg1 in
|
||||
let convertedcode, m = c_ss_sa a2 m convertedcode partialresreg2 in
|
||||
(BRegOp (Sub, partialresreg1, partialresreg2, register) :: convertedcode, m)
|
||||
)
|
||||
)
|
||||
| SimpleTimes (a1, a2) -> (
|
||||
match (a1, a2) with
|
||||
| (SimpleInteger (i), a)
|
||||
| (a, SimpleInteger (i)) -> (
|
||||
let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a m convertedcode partialresreg in
|
||||
(BImmOp (MultI, partialresreg, i, register) :: convertedcode, m)
|
||||
)
|
||||
| (_, _) -> (
|
||||
let partialresreg1, m, _partialresvar1 = RegisterMap.get_fresh_register m in
|
||||
let partialresreg2, m, _partialresvar2 = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a1 m convertedcode partialresreg1 in
|
||||
let convertedcode, m = c_ss_sa a2 m convertedcode partialresreg2 in
|
||||
(BRegOp (Mult, partialresreg1, partialresreg2, register) :: convertedcode, m)
|
||||
)
|
||||
)
|
||||
| SimpleDivision (a1, a2) -> (
|
||||
match (a1, a2) with
|
||||
| (a, SimpleInteger (i)) -> (
|
||||
let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a m convertedcode partialresreg in
|
||||
(BImmOp (DivI, partialresreg, i, register) :: convertedcode, m)
|
||||
)
|
||||
| (_, _) -> (
|
||||
let partialresreg1, m, _partialresvar1 = RegisterMap.get_fresh_register m in
|
||||
let partialresreg2, m, _partialresvar2 = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a1 m convertedcode partialresreg1 in
|
||||
let convertedcode, m = c_ss_sa a2 m convertedcode partialresreg2 in
|
||||
(BRegOp (Div, partialresreg1, partialresreg2, register) :: convertedcode, m)
|
||||
)
|
||||
)
|
||||
| SimpleModulo (a1, a2) -> (
|
||||
match (a1, a2) with
|
||||
| (a, SimpleInteger (i)) -> (
|
||||
let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a m convertedcode partialresreg in
|
||||
(BImmOp (ModI, partialresreg, i, register) :: convertedcode, m)
|
||||
)
|
||||
| (_, _) -> (
|
||||
let partialresreg1, m, _partialresvar1 = RegisterMap.get_fresh_register m in
|
||||
let partialresreg2, m, _partialresvar2 = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a1 m convertedcode partialresreg1 in
|
||||
let convertedcode, m = c_ss_sa a2 m convertedcode partialresreg2 in
|
||||
(BRegOp (Mod, partialresreg1, partialresreg2, register) :: convertedcode, m)
|
||||
)
|
||||
)
|
||||
| SimplePower (a1, a2) -> (
|
||||
match (a1, a2) with
|
||||
| (a, SimpleInteger (i)) -> (
|
||||
let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a m convertedcode partialresreg in
|
||||
(BImmOp (PowI, partialresreg, i, register) :: convertedcode, m)
|
||||
)
|
||||
| (_, _) -> (
|
||||
let partialresreg1, m, _partialresvar1 = RegisterMap.get_fresh_register m in
|
||||
let partialresreg2, m, _partialresvar2 = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a1 m convertedcode partialresreg1 in
|
||||
let convertedcode, m = c_ss_sa a2 m convertedcode partialresreg2 in
|
||||
(BRegOp (Pow, partialresreg1, partialresreg2, register) :: convertedcode, m)
|
||||
)
|
||||
)
|
||||
| SimplePowerMod (_a1, _a2, _a3) -> failwith "Not implemented Powermod"
|
||||
| SimpleRand (a) -> (
|
||||
let partialresreg, m, _partialresvar = RegisterMap.get_fresh_register m in
|
||||
let convertedcode, m = c_ss_sa a m convertedcode partialresreg in
|
||||
(URegOp (Rand, partialresreg, register) :: convertedcode, m)
|
||||
)
|
||||
|
||||
let convert_ss
|
||||
(m: RegisterMap.m)
|
||||
(value: CfgImp.SimpleStatements.t list)
|
||||
(node: Cfg.Node.t)
|
||||
(risccode: RISCSimpleStatements.t list Cfg.NodeMap.t)
|
||||
: RISCSimpleStatements.t list Cfg.NodeMap.t * RegisterMap.m =
|
||||
let instructions, m = List.fold_right (fun code (convertedcode, m) ->
|
||||
c_ss_t code m convertedcode) value ([], m) in
|
||||
(Cfg.NodeMap.add node instructions risccode, m)
|
||||
|
||||
let helper (c: CfgImp.SimpleStatements.t list Cfg.NodeMap.t) (m: RegisterMap.m) : RISCSimpleStatements.t list Cfg.NodeMap.t =
|
||||
let risccode, _ = Cfg.NodeMap.fold (fun node value (risccode, m) -> convert_ss m value node risccode) c (Cfg.NodeMap.empty, m) in
|
||||
risccode
|
||||
|
||||
let convert_content (c: CfgImp.SimpleStatements.t list Cfg.NodeMap.t) : RISCSimpleStatements.t list Cfg.NodeMap.t =
|
||||
helper c RegisterMap.empty
|
||||
|
||||
let convert (prg: CfgImp.SSCfg.t) : RISCCfg.t =
|
||||
match prg with
|
||||
{ empty: bool;
|
||||
nodes: Cfg.NodeSet.t;
|
||||
edges: (Cfg.Node.t * (Cfg.Node.t option)) Cfg.NodeMap.t;
|
||||
reverseEdges: (Cfg.Node.t list) Cfg.NodeMap.t;
|
||||
inputVal: int option;
|
||||
inputOutputVar: (string * string) option;
|
||||
initial: Cfg.Node.t option;
|
||||
terminal: Cfg.Node.t option;
|
||||
content: CfgImp.SimpleStatements.t list Cfg.NodeMap.t
|
||||
} -> { empty = empty;
|
||||
nodes = nodes;
|
||||
edges = edges;
|
||||
reverseEdges = reverseEdges;
|
||||
inputVal = inputVal;
|
||||
inputOutputVar = inputOutputVar;
|
||||
initial = initial;
|
||||
terminal = terminal;
|
||||
content = convert_content content;
|
||||
}
|
||||
53
lib/miniImp/CfgRISC.mli
Normal file
53
lib/miniImp/CfgRISC.mli
Normal file
@ -0,0 +1,53 @@
|
||||
module RISCSimpleStatements : sig
|
||||
type register = {
|
||||
index: int
|
||||
}
|
||||
|
||||
type t =
|
||||
| Nop
|
||||
| BRegOp of brop * register * register * register
|
||||
| BImmOp of biop * register * int * register
|
||||
| URegOp of urop * register * register
|
||||
| Load of register * register
|
||||
| LoadI of register * int
|
||||
| Store of register * register
|
||||
and brop =
|
||||
| Add
|
||||
| Sub
|
||||
| Mult
|
||||
| Div
|
||||
| Mod
|
||||
| Pow
|
||||
| And
|
||||
| Or
|
||||
| Eq
|
||||
| Less
|
||||
| LessEq
|
||||
| More
|
||||
| MoreEq
|
||||
and biop =
|
||||
| AddI
|
||||
| SubI
|
||||
| MultI
|
||||
| DivI
|
||||
| ModI
|
||||
| PowI
|
||||
| AndI
|
||||
| OrI
|
||||
| EqI
|
||||
| LessI
|
||||
| LessEqI
|
||||
| MoreI
|
||||
| MoreEqI
|
||||
and urop =
|
||||
| Not
|
||||
| Copy
|
||||
| Rand
|
||||
|
||||
val pp : out_channel -> t -> unit
|
||||
val pplist : out_channel -> t list -> unit
|
||||
end
|
||||
|
||||
module RISCCfg : Cfg.C with type elt = RISCSimpleStatements.t
|
||||
|
||||
val convert : CfgImp.SSCfg.t -> RISCCfg.t
|
||||
@ -10,7 +10,7 @@
|
||||
(library
|
||||
(name miniImp)
|
||||
(public_name miniImp)
|
||||
(modules Lexer Parser Types Semantics CfgImp)
|
||||
(modules Lexer Parser Types Semantics CfgImp CfgRISC)
|
||||
(libraries cfg utility menhirLib))
|
||||
|
||||
(include_subdirs qualified)
|
||||
|
||||
Reference in New Issue
Block a user