elvis efa6ed21c9 Added While loop to RISC

2024-12-02 14:26:05 +01:00

..

cfg

Fixes wrong order for conversion

2024-12-02 00:45:24 +01:00

exercises

separated into modules, added parser and lexer for miniImp

2024-11-13 21:50:44 +01:00

miniFun

Compleating assignment for interpreter, modified grammars, fixed tests

2024-11-16 15:40:00 +01:00

miniImp

Added While loop to RISC

2024-12-02 14:26:05 +01:00

utility

RISC code output

2024-12-01 12:55:20 +01:00